The present invention is related to a system on a chip.
Electronic devices or systems have some kind of initialization mechanism. In general, slave systems or sub-systems are reset through a dedicated reset pin. The reset signal is routed to important memory elements and forces initial conditions. Some systems have internal reset circuits that generate an internal reset pulse upon power-on. Some sub-modules of a system, like a CPU, are also selectively reset. Various other application reset resources are commonly used such as software or watchdogs resets. Various systems require some combinations of reset. However, all these methods have never been assembled into a single architecture that serves the stringent requirements of configurable system-on-chip.
A method to provide hierarchical reset capabilities for a configurable system on a chip is disclosed. The method includes determining a plurality of reset functions, and establishing a reset hierarchy among the plurality of reset functions.
These features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.